View MMC2080VF001_1519962.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mmc2080/2075/d rev. 0 , 10/1999 this document contains information on a new product. specifications and information herein are subject to change without notice. semiconductor products sector ? motorola, inc., 1999. all rights reserved. mmc2080/2075 advance information mmc2080/2075 integrated processor with roaming flex? decoder part 1 introduction the mmc2080/2075 is designed to provide the messaging and paging marketplace with a powerful and flexible solution to carry communications design into the next millennium. the mmc2080 integrates two of motorola?s most successful product families, mcore? and the roaming flex? alphanumeric decoders, a combination that will set a new standard in the communications industry. except for the flex decoder, the mmc2075 offers all features of the mmc2080. both the the mmc2080/2075 are members of the low-power, high-performance mcore family of 32-bit microcontroller units (mcus). the mcore is a streamlined execution engine that provides many of the performance enhancements found in mainstream reduced instruction set computers (riscs). combining performance, speed, and cost efficiency in a compact, low-power design, the mcore microrisc architecture is a natural solution for applications where battery life and systems cost are critical design goals. given that a total system?s components and processor core determine its power consumption, the instruction set architecture (isa) for the mcore is designed to optimize the trade-off between performance and total power consumption. the result is system-wide reduction of total energy consumption with maintenance of acceptable performance levels. memory power consumption (both on-chip and external) is a major factor in system energy consumption. by adopting 16-bit instruction encoding, and thus significantly decreasing the memory bandwidth needed for a high rate of instruction execution, the mmc2080/2075 minimizes the overhead of memory system energy consumption. the mmc2080/2075 also reduces power consumption by coupling a fully static design with dynamic power management and low-voltage operation. versatile power management is achieved through automatic power downs of any internal functional blocks not needed on a clock-by-clock basis. power conservation modes are also provided for absolute power conservation. a table of contents for this document appears on the following page. figure 1 on page 3 and figure 2 on page 4 provide simplified block diagrams of the mmc2080/2075.
2 mmc2080/2075 technical data preliminary part 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 conventions and terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 integrated roaming flex protocol and the mmc2080 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 target applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 part 2 signal and connection descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 mmc2080/2075 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 tables of signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 part 3 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1 general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 part 4 pin-out and package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 bga details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2 pga details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3 ordering drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 part 5 design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 heat dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 electrical design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
introduction 3 preliminary figure 1. mmc2080/2075 144 block diagram (144-pin package) eb [1:0] bw8 we ta abort busclk mpe4/lock mpe3/mosi mpe2/miso mpe1/ss mpe0/sclk mpb[7:4]/row[3:0] mpb[3:0]/col[3:0] mpa[5:0] lobat exts[1:0] clkout symclk s[7:1] s0/ifin mpc1/tic0 mpc0/toc0 reset rstout mpc5/ucts mpc4/urts mpc7/urxd mpc6/utxd mpc3/tic1 mpc2/toc1 de tms tck tdi tdo trst cxfc uclk mldy xtal extal bgnt breq i/o i/o jtag jtag system bus external bus bridge (mpio) osc cpu once por pll apb 6k ram 96k rom intc arbiter melody cnfg keypad flex spi0 mpio sim sci timer1 timer0 spi1-fsc peripheral bus mmc2080 only oe d[7:0] a[21:0] mpd[7:0]/d[15:8] irq sel [2:0], sel3 xboot
4 mmc2080/2075 technical data preliminary figure 2. mmc2080/2075 dvl block diagram (208-pin package) a[21:0] eb [1:0] dvleb [1:0] bw8 we ta tea abort busclk mpe4/lock mpe3/mosi mpe2/miso mpe1/ss mpe0/sclk mpb[7:4]/row[3:0] mpb[3:0]/col[3:0] mpa[5:0] lobat exts[1:0] clkout symclk s[7:1] s0/ifin mpc1/tic0 mpc0/toc0 reset rstout mpc5/ucts mpc4/urts mpc7/urxd mpc6/utxd mpc3/tic1 mpc2/toc1 de tms tck tdi tdo trst cxfc uclk mldy xtal extal irq bgnt breq i/o i/o jtag jtag system bus external bus bridge (mpio) osc cpu once por pll apb 6k ram 96k rom intc arbiter melody cnfg keypad flex spi0 mpio sim sci timer1 timer0 spi1-fsc peripheral bus mmc2080 only oe dstat[5:0] dvlmx sel [2:0], sel3 dvlsel xboot dvl [1:0] d[7:0] d[31:16] mpd[7:0]/d[15:8] highz pull_en tc[2:0] shs
conventions and terminology introduction 5 preliminary 1.1 conventions and terminology this document uses the following conventions: overbar is used to indicate a signal that is active when pulled low: for example, reset . logic level one is a voltage that corresponds to boolean true (1) state. logic level zero is a voltage that corresponds to boolean false (0) state. to set a bit or bits means to establish logic level one. to clear a bit or bits means to establish logic level zero. a signal is an electronic construct whose state or changes in state convey information. a pin is an external physical connection. the same pin can be used to connect a number of signals. asserted means that a discrete signal is in active logic state. ? active low signals change from logic level one to logic level zero. ? active high signals change from logic level zero to logic level one. deasserted means that an asserted discrete signal changes logic state. ? active low signals change from logic level zero to logic level one. ? active high signals change from logic level on to logic level zero. lsb means least significant bit or bits . msb means most significant bit or bits . references to low and high bytes or words are spelled out. please refer to the examples in table 1. table 1. data conventions signal/symbol logic state signal state voltage pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
6 mmc2080/2075 technical data preliminary features 1.2 features the mmc2080/2075 offers the following suite of features. m core ? risc processor ? 32-bit load/store m core risc architecture ? fixed 16-bit instruction length ? 16-entry 32-bit general-purpose register file ? 32-bit internal address and data buses ? efficient, four-stage, fully interlocked execution pipeline ? single-cycle execution for most instructions; two cycles for branches and memory accesses ? special branch, byte, and bit manipulation instructions ? support for byte, halfword, and word memory accesses ? fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register file integrated roaming flex alphanumeric decoder (mmc2080 only) ? flex paging protocol signal processor ? 1600, 3200, and 6400 bits per second (bps) decoding ? highly programmable receiver control ? flex message fragmentation and group messaging support ? ssid and nid roaming support ? internal demodulator and data slicer ? improved battery savings via partial address correlation and intermittent receiver clock ? full support for revision g1.9 of the flex protocol ? external cap code access through parallel or serial flash/prom on-chip memory ? 24 k 32 cpu rom (96 k) ? 1.5 k 32 cpu ram (6 k) on-chip peripherals ? asynchronous serial communications interface (sci) with irda capability ? synchronous serial peripheral interface (spi) ? frequency synthesizer controller (fsc) ? melody generator ? 4 4 keypad interface ? multipurpose i/o ports (mpio) ? two 16-bit general purpose timers ? time-of-day (tod) timer ? watchdog timer ? vectored interrupt controller with 16 programmable priority levels
features introduction 7 preliminary ? oscillator and pll with software selectable speeds ? amba peripheral bridge depipelines system bus for simpler peripheral bus ? 8/16-bit external system bus with 22-bit address bus operating features ? processor operation to 10 mhz over full operating range ? low-power modes ? once ? (on-chip emulation) debug module ? voltage range 1.8 v to 3.6 v; temperature range -20 c to 85 c ? chip-select outputs for four external devices (4 mbyte per chip select, 16 mbyte directly addressable) ? programmable wait states for external accesses ? external boot option ? external bus interface that accepts internal, half-word, and byte transfers ? external device that may become system bus master development tools ? development option (different package) that adds select to bypass internal rom ? development option (different package) that extends external bus to 32 bits ? external bus that can display internal transfers
8 mmc2080/2075 technical data preliminary integrated roaming flex protocol and the mmc2080 1.3 integrated roaming flex protocol and the mmc2080 the mmc2080 integrates several field-proven technologies, providing a versatile roaming flex solution. the mmc2080 operates the integrated flex decoder in an efficient power-consumption mode, allowing the cpu to operate in a low-power mode when monitoring for message information. the roaming flex protocol is a multichannel, high-performance protocol that leading service providers worldwide have adopted as a de facto standard for roaming paging. roaming flex protocol gives service providers increased capacity, added reliability, enhanced pager battery performance, and the ability to control a pll- synthesized receiver and to receive paging messages from a list of paging channels. finally, the mmc2080 gives the service provider an upward migration path that is completely transparent to the end user. 1.4 target applications the mmc2080/2075 is intended for use in wireless and paging applications. the mmc2080 is designed for applications needing an m core cpu coupled with a roaming flex decoder. the mmc2075 is intended for applications requiring the processing power and flexibility of the m core cpu. 1.5 product documentation the three documents listed in table 2 are required for a complete description of the mmc2080/2075 and are necessary to design properly with the part. documentation is available from a local motorola distributor, a motorola semiconductor products sector sales office, a motorola literature distribution center, or the world wide web. see the last page of this document for contact information. 1.6 ordering information table 3 lists the information you need to supply when placing an order. consult a motorola semiconductor products sector sales office or authorized distributor to determine availability and to order parts. table 2. mmc2080/2075 documentation document name description of contents order number m?core reference manual detailed description of the m?core mcu and instruction set mcorerm/ad mmc2080/2075 u ser ? s manual detailed description of the mmc2080/2075 memory, peripherals, and interfaces mmc2080/2075um/d mmc2080/2075 technical data mmc2080/2075 pin and package descriptions; electrical and timing specifications mmc2080/2075/d table 3. mmc2080/2075 ordering information part supply voltage package type pin count order number mmc2080 3 v 12 mm x 12 mm map bga 144 MMC2080VF001 mmc2075 3 v 12 mm x 12 mm map bga 144 mmc2075vf001 mmc2080 3 v 43 mm x 43 mm ceramic pga 208 contact factory development use only mmc2075 3 v 43 mm x 43 mm ceramic pga 208
mmc2080/2075 pin descriptions signal and connection descriptions 9 preliminary part 2 signal and connection descriptions the pins and signals of the mmc2080/2075 are described in the following sections. figure 3 on page 10 and figure 4 on page 11 are top and bottom views, respectively, of the 12 mm x 12 mm map ball grid array (bga) package, and figure 5 on page 12 and figure 6 on page 13 are top and bottom views, respectively, of the 43 mm x 43 mm ceramic pin grid array (pga) package, showing the pin-outs. table 4 on page 14 and table 5 on page 17 list the pins by number and signal name. figure 7 on page 21 is a representational pin-out of the chip, grouping the signals by their function. table 6 on page 20 identifies the number of signals for each group and refers to table 8 on page 23 through table 20 on page 27, which are organized according to signal type and give a brief description of each signal pin. 2.1 mmc2080/2075 pin descriptions the following section provides information about the available packages for this product, including diagrams of the package pin-outs and tables describing how the signals of the mmc2080/2075 are allocated. there are two packages for each part: the 144-pin i/o, std small ball (smball) mold array process (map) ball grid array (bga), 12 mm x 12 mm package. table 4 on page 14 identifies the signal associated with each pin. the 208-pin i/o, pga, 43 mm x 43 mm ceramic package. table 5 on page 17 identifies the signal associated with each pin.
10 mmc2080/2075 technical data preliminary mmc2080/2075 pin descriptions figure 3. mmc2080/2075 bga (144-pin) top view 1 13 12 11 10 9 8 7 6 5 4 3 2 a b c d e f g h j k l m n v ss i/o s2* lobat* clkout* v dd i/o mpb5/ row1 eb1 mpb2/ col2 mpb0/ col0 v dd i/o sel1 v ss i/o v ss core mpb7/ row3 s1* v ss i/o mldy exts1* mpb6/ row2 bw8 abort eb0 v dd core sel0 s7* s4* irq symclk exts0* v dd i/o v ss i/o mpa0 mpb4/ row0 mpb3/ col3 mpb1/ col1 ta sel2 s6* s3* v dd core s0/ifin mpe4/ lock v dd core mpe3/ mosi d0 mpa1 v ss core oe we sel3 s5* xboot busclk v dd osc extal xtal v ss osc v ss i/o d2 d1 v dd i/o v dd pll cxfc v ss pll a21 mpa3 mpa2 v dd i/o mpa5 a20 a19 a18 v ss core mpa4 d3 d4 v ss i/o a16 a17 v dd i/o breq d8 d9 v dd i/o v ss core mpe1/ ss mpe2/ miso v ss i/o a15 d5 d10 bgnt d11 a12 mpe0/ sclk a13 a14 d12 v dd core tdi a1 mpc0/ toc0 mpc5/ ucts v dd core a8 d6 a10 v ss i/o v dd i/o a11 d7 d13 tdo v ss core mpc3/ tic1 a5 mpc6/ utxd v dd i/o d14 test rstout v dd i/o uclk d15 v ss i/o trst a2 mpc2/ toc1 a3 mpc7/ urxd a7 v dd i/o a9 de reset v ss i/o tck tms a0 mpc1/ tic0 v ss i/o a4 mpc4/ urts a6 top view * signal available only in 2080
mmc2080/2075 pin descriptions signal and connection descriptions 11 preliminary figure 4. mmc2080/2075 bga (144-pin) bottom view 1 1312111098765432 a b c d e f g h j k l m n v ss i/o s2 * lobat* clkout* v dd i/o mpb5/ row1 eb1 mpb2/ col2 mpb0/ col0 v dd i/o sel1 v ss i/o v ss core mpb7/ row3 s1* v ss i/o mldy exts1* mpb6/ row2 bw8 abort eb0 v dd core sel0 s7* s4* irq symclk exts0* v dd i/o v ss i/o mpa0 mpb4/ row0 mpb3/ col3 mpb1/ col1 ta sel2 s6* s3* v dd core s0/ifin mpe4/ lock v dd core mpe3/ mosi d0 mpa1 v ss core oe we sel3 s5* xboot busclk v dd osc extal xtal v ss osc v ss i/o d2 d1 v dd i/o v dd pll cxfc v ss pll a21 mpa3 mpa2 v dd i/o mpa5 a20 a19 a18 v ss core mpa4 d3 d4 v ss i/o a16 a17 v dd i/o breq d8 d9 v dd i/o v ss core mpe1/ ss mpe2/ miso v ss i/o a15 d5 d10 bgnt d11 a12 mpe0/ sclk a13 a14 d12 v dd core tdi a1 mpc0/ toc0 mpc5/ ucts v dd core a8 d6 a10 v ss i/o v dd i/o a11 d7 d13 tdo v ss core mpc3/ tic1 a5 mpc6/ utxd v dd i/o d14 test rstout v dd i/o uclk d15 v ss i/o trst a2 mpc2/ toc1 a3 mpc7/ urxd a7 v dd i/o a9 de reset v ss i/o tck tms a0 mpc1/ tic0 v ss i/o a4 mpc4/ urts a6 bottom view * signal available only in 2080
12 mmc2080/2075 technical data preliminary mmc2080/2075 pin descriptions figure 5. mmc2080/2075 pga (208-pin) top view 1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 a b c d e f g h j k l m n p r t u v ss i/o s2 * lobat* clkout* v dd i/o mpb5/ row1 eb1 mpb2/ col2 mpb0/ col0 v dd i/o sel1 v ss i/o v ss core mpb7/ row3 s1* v ss i/o mldy exts1* mpb6/ row2 bw8 abort eb0 v dd core sel0 s7* s4* irq symclk exts0* v dd i/o v ss i/o mpa0 mpb4/ row0 mpb3/ col3 mpb1/ col1 ta sel2 s6* s3* v dd core s0/ ifin mpe4/ lock v dd core mpe3/ mosi d0 mpa1 v ss core oe we sel3 s5* xboot busclk v dd osc extal xtal v ss osc v ss i/o d2 d1 v dd i/o v dd pll cxfc v ss pll a21 mpa3 mpa2 v dd i/o mpa5 a20 a19 a18 v ss core mpa4 d3 d4 v ss i/o a16 a17 v dd i/o breq d8 d9 v dd i/o v ss core mpe1/ ss mpe2/ miso v ss i/o a15 d5 d10 bgnt d11 a12 mpe0/ sclk a13 a14 d12 v dd core tdi a1 mpc0/ toc0 mpc5/ ucts v dd core a8 d6 a10 v ss i/o v dd i/o a11 d7 d13 tdo v ss core mpc3/ tic1 a5 mpc6/ utxd v dd i/o d14 test rstout uclk d15 v ss i/o trst a2 mpc2/ toc1 a3 mpc7/ urxd a7 v dd i/o a9 de reset v ss i/o tck tms a0 mpc1/ tic0 v ss i/o a4 mpc4/ urts a6 d17 d18 d19 d20 d21 d22 d23 d24 d25 tc0 highz d26 d27 d28 d29 d30 d31 shs tc1 tc2 dstat0 dstat1 dstat2 dstat3 dstat4 dstat5 dvlmx dvlsel dvl0 dvl1 dvleb0 tea dvleb1 d16 pull_en nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc top view * signal available only in 2080
mmc2080/2075 pin descriptions signal and connection descriptions 13 preliminary figure 6. mmc2080/2075 pga (208-pin) bottom view 1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 a b c d e f g h j k l m n p r t u v ss i/o s2 * lobat* clkout v dd i/o mpb5/ row1 eb1 mpb2/ col2 mpb0/ col0 v dd i/o sel1 v ss i/o v ss core mpb7/ row3 s1* v ss i/o mldy exts1* mpb6/ row2 bw8 abort eb0 v dd core sel0 s7* s4* irq symclk exts0* v dd i/o v ss i/o mpa0 mpb4/ row0 mpb3/ col3 mpb1/ col1 ta sel2 s6* s3* v dd core s0/ifin mpe4/ lock v dd core mpe3/ mosi d0 mpa1 v ss core oe we sel3 s5* xboot busclk v dd osc extal xtal v ss osc v ss i/o d2 d1 v dd i/o v dd pll cxfc v ss pll a21 mpa3 mpa2 v dd i/o mpa5 a20 a19 a18 v ss core mpa4 d3 d4 v ss i/o a16 a17 v dd i/o breq d8 d9 v dd i/o v ss core mpe1/ ss mpe2/ miso v ss i/o a15 d5 d10 bgnt d11 a12 mpe0/ sclk a13 a14 d12 v dd core tdi a1 mpc0/ toc0 mpc5/ ucts v dd core a8 d6 a10 v ss i/o v dd i/o a11 d7 d13 tdo v ss core mpc3/ tic1 a5 mpc6/ utxd v dd i/o d14 test rstout uclk d15 v ss i/o trst a2 mpc2/ toc1 a3 mpc7/ urxd a7 v dd i/o a9 de reset v ss i/o tck tms a0 mpc1/ tic0 v ss i/o a4 mpc4/ urts a6 d17 d18 d19 d20 d21 d22 d23 d24 d25 tc0 highz d26 d27 d28 d29 d30 d31 shs tc1 tc2 dstat0 dstat1 dstat2 dstat3 dstat4 dstat5 dvlmx dvlsel dvl0 dvl1 dvleb0 tea dvleb1 d16 pull_en nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc bottom view ** * signal available only in 2080
14 mmc2080/2075 technical data preliminary mmc2080/2075 pin descriptions table 4. mmc2080/2075 bga (144-pin) signal id by pin number (sheet 1 of 3) pin number signal name pin number signal name a1 vss i/o g10 a20 a2 mpb5/row1 g11 a19 a3 bw8 g12 a18 a4 mpb2/col2 g13 vss core a5 mpb0/col0 h1 vss i/o a6 vdd i/o h2 d8 a7 sel1 h3 d9 a8 vss i/o h4 vdd i/o a9 vss core h10 a16 a10 s2 (2080 only) h11 a17 a11 lobat (2080 only) h12 vdd i/o a12 clkout (2080 only) h13 breq a13 vdd i/o j1 vss core b1 mpb7/row3 j2 d5 b2 mpb6/row2 j3 d10 b3 bw8 j4 bgnt b4 abort j10 mpe1/ss b5 eb0 j11 mpe2/mis0 b6 vdd core j12 vss i/o b7 sel0 j13 a15 b8 s7 (2080 only) k1 d11 b9 s4 (2080 only) k2 d12 b10 s1 (2080 only) k3 vdd core b11 vss i/o k4 tdi b12 mldy k5 a1 b13 exts1 (2080 only) k6 mpc0/toc0 c1 irq k7 mpc5/ucts c2 mpa0 k8 vdd core
mmc2080/2075 pin descriptions signal and connection descriptions 15 preliminary c3 mpb4/row0 k9 a8 c4 mpb3/col3 k10 a12 c5 mpb1/col1 k11 mpe0/sclk c6 ta k12 a13 c7 sel2 k13 a14 c8 s6 (2080 only) l1 d6 c9 s3 (2080 only) l2 d7 c10 symclk (2080 only) l3 d13 c11 exts0 (2080 only) l4 tdo c12 vdd i/o l5 vss core c13 vss i/o l6 mpc3/tic1 d1 vdd core l7 a5 d2 d0 l8 mpc6/utxd d3 mpa1 l9 vdd i/o d4 vss core l10 a10 d5 oe l11 vss i/o d6 we l12 vdd i/o d7 sel3 l13 a11 d8 s5 (2080 only) m1 d14 d9 xboot m2 d15 d10 s0/ifin (2080 only) m3 vss i/o d11 mpe4/lock m4 trst d12 vdd core m5 a2 d13 mpe3/mosi m6 mpc2/toc1 e1 busclk m7 a3 e2 vss i/o m8 mpc7/urxd e3 d2 m9 a7 e4 d1 m10 test table 4. mmc2080/2075 bga (144-pin) signal id by pin number (sheet 2 of 3) pin number signal name pin number signal name
16 mmc2080/2075 technical data preliminary mmc2080/2075 pin descriptions e10 vdd osc m11 rstout e11 extal m12 vdd i/o e12 xtal m13 uclk e13 vss osc n1 vdd i/o f1 vdd i/o n2 tck f2 mpa3 n3 tms f3 mpa2 n4 a0 f4 vdd i/o n5 mpc1/tic0 f10 vdd pll n6 vss i/o f11 cxfc n7 a4 f12 vss pll n8 mpc4/urts f13 a21 n9 a6 g1 mpa5 n10 a9 g2 mpa4 n11 de g3 d3 n12 reset g4 d4 n13 vss i/o table 4. mmc2080/2075 bga (144-pin) signal id by pin number (sheet 3 of 3) pin number signal name pin number signal name
mmc2080/2075 pin descriptions signal and connection descriptions 17 preliminary table 5. mmc2080/2075 pga (208-pin) signal id by pin number (sheet 1 of 4) pin number signal name pin number signal name a1 mpb6/row2 j4 d3 a2 mpb4/row0 j14 a21 a3 bw8 j15 a20 a4 mpb2/col2 j16 vss core a5 mpb0/col0 j17 vss pll a6 ta k1 d8 a7 dvleb1 k2 vss i/o a8 sel3 k3 d9 a9 sel1 k4 d21 a10 vss i/o k14 a17 a11 dvleb0 k15 a15 a12 vss core k16 breq a13 s2 (2080 only) k17 tc1 a14 s0/ifin (2080 only) l1 vdd i/o a15 dvlmx l2 vss core a17 mldy l3 d10 b3 mpb5/row1 l4 bgnt b4 pull_en l14 a14 b5 mpb3/col3 l15 mpe2/mis0 b6 mpb1/col1 l16 a18 b7 we l17 a19 b8 sel2 m1 d22 b9 s7 (2080 only) m2 d23 b10 s5 (2080 only) m3 d12 b11 s6 (2080 only) m4 d25 b12 s3 (2080 only) m14 a11 b13 dvl1 m15 mpe0/sclk b14 lobat (2080 only) m16 a16
18 mmc2080/2075 technical data preliminary mmc2080/2075 pin descriptions b17 exts0 (2080 only) m17 vdd i/o c1 irq n1 d5 c5 d16 n2 d24 c6 abort n3 d6 c7 eb0 n14 uclk c8 vdd i/o n15 vdd i/o c9 tea n16 mpe1/ss c10 xboot n17 vss i/o c11 s1 (2080 only) p1 d11 c12 dvlo p2 d7 c13 vss i/o p3 tck c14 vdd i/o p4 tc0 c16 exts1 (2080 only) p5 tck c17 dstat4 p6 tc0 d1 vdd core p7 d26 d2 mpa1 p8 vsscore d3 vss i/o p9 a3 d4 eb1 p10 mpc6/utxd d5 oe p11 a8 d6 vdd core p12 de d7 oe p15 vss i/o d8 vddc ore p16 a12 d9 sel0 p17 a13 d10 s4 (2080 only) r1 vdd core d11 symclk (2080 only) r2 d14 d12 dvlsel r4 vdd i/o d13 clkout (2080 only) r5 vss i/o d16 dstat5 r6 highz table 5. mmc2080/2075 pga (208-pin) signal id by pin number (sheet 2 of 4) pin number signal name pin number signal name
mmc2080/2075 pin descriptions signal and connection descriptions 19 preliminary d17 dstat1 r7 d27 e1 busclk r8 a0 e2 d2 r9 mpc2/toc1 e3 mpa0 r10 mpc4/urts e4 mpb7/row3 r11 a7 e15 vdd i/o r12 test e16 vss i/o r13 rstout e17 mpe3/mosi t1 d13 f1 d17 t4 tms f2 mpa2 t5 tdo f3 d0 t6 a1 f4 vss core t7 mpc1/tic0 f14 dstat3 t8 d28 f15 dstat2 t9 mpc0/toc0 f16 dstat0 t10 a5 f17 vdd osc t11 vdd core g1 mpa4 t12 vdd i/o g2 vdd i/o t13 a10 g3 vss i/o t14 d31 g4 d1 t15 reset g14 mpe4/lock t16 shs g15 vdd core u1 d15 g16 tc2 u4 tdi g17 xtal u5 trst h1 mpa5 u6 a2 h2 d18 u7 mpc3/tic1 h3 vdd i/o u8 vss i/o h4 mpa3 u9 a4 table 5. mmc2080/2075 pga (208-pin) signal id by pin number (sheet 3 of 4) pin number signal name pin number signal name
20 mmc2080/2075 technical data preliminary tables of signals 2.2 tables of signals the mmc2080 input and output signals are organized into functional groups in table 6 and in figure 7 on page 21. table 7 on page 22 displays data relating to i/o cell names, including descriptions and the availability of hi-z impedance, pull-up resistors, and high drive-current capability. table 8 on page 23 through table 20 on page 27 are organized according to signal type and give a brief description of each signal pin. package type is indicated as ? n ? for the 144-pin normal-function package. all pins are available in the 208-pin development extensions package. h14 extal u10 mpc5/ucts h15 vss osc u11 mpc7/urxd h16 cxfc u12 d29 h17 vdd pll u13 a6 j1 d4 u14 a9 j2 d19 u15 d30 j3 d20 u16 vss i/o table 6. mmc2080 signal functional group organization functional group number of signals detailed description arbitration signals 2 table 20 on page 27 external system bus signals 52 table 8 on page 23 development extensions (208-pin package only) 34 table 9 on page 24 flex signals 13 table 10 on page 25 fsc/spi signals 5 table 11 on page 25 sci signals 5 table 12 on page 25 timer signals 4 table 13 on page 26 melody generator signals 1 table 14 on page 26 keypad signals 8 table 15 on page 26 dedicated mpio signals 6 table 16 on page 26 sim signals 2 table 17 on page 26 jtag/once signals 6 table 18 on page 27 clock and power 40 table 19 on page 27 table 5. mmc2080/2075 pga (208-pin) signal id by pin number (sheet 4 of 4) pin number signal name pin number signal name
tables of signals signal and connection descriptions 21 preliminary figure 7. mmc2080 signal group organization breq bgnt mpd[7:0]/d[15:8] d[7:0] a[21:0] eb0 ?1 bw8 we oe ta abort busclk sel0 ?3 xboot irq d[31:16] dvleb0 ?1 dvl0 ?1 dvlsel dstat0?5 dvlmx tc0?2 tea highz pull_en lobat exts0?1 clkout symclk s1?7 s0/ifin mpe4/lock mpe3/mosi mpe2/miso mpe1/ss mpe0/sclk mpc7/urxd mpc6/utxd mpc5/ucts mpc4/urts uclk mpc3/tic1 mpc2/toc1 mpc1/tic0 mpc0/toc0 mldy mpb[7:4]/row[3:0] mpb[3:0]/col[3:0] mpa[5:0] v dd reset rstout tms tck tdi tdo trst de extal xtal cxfc v dd core[5] v ss core[5] iov dd [11] iov ss [11] oscv dd oscv ss pllv dd pllv ss arbitration flex development external arbitration request arbitration grant high-order data bus low-order data bus address byte enable bus width (8-bit) data direction output enable transfer acknowledge data transfer abort external bus clock external device select external boot interrupt request extension byte enable development mode development select development status status output select transfer code transfer error acknowledge tri-state disable pull-up enable low battery extension symbol clock output symbol clock serial port serial port synthesizer lock master in/slave out master out/slave in slave select serial clock receive data transmit data request-to-send uart clock timer1 input capture timer1 output capture timer0 input capture timer0 output capture generator waveform row detect column detect master reset reset output test mode select tes t c loc k test data in test data out debug enable oscillator circuit input oscillator circuit output pll filter capacitor core power i/o pad power i/o pad ground oscillator power clear-to-send tap reset core ground oscillator ground pll power pll ground mmc2080 system bus signals extensions (208-pin package) signals fsc/spi signals signals timer signals melody generator signal keypad signals mpio signals sim signals jtag/once signals clock and power sci signals shs show cycle strobe
22 mmc2080/2075 technical data preliminary tables of signals table 7. i/o cell description i/o cell name description hi-z pull-up high drive capable otp tri-state output with selectable drive strength; always enabled with strong drive except during jtag hi-z command or unless otherwise stated yn y inhp input with hysteresis n n n inhpp inhp with selectable pull-up enable n y n iohp inhp and otp y n y iohpph inhpp and otp y y y swiop high-current iohpph y y y ain/aot analog input/output (same cell) n n n
tables of signals signal and connection descriptions 23 preliminary table 8. external system bus signals signal name dir n i/o cell description mpd[7:0]/d[15:8] i/o y iohpph high-order data bus ? may be used as general i/o when the data bus is configured as an 8-bit bus. output drivers are disabled and pull-up resistors are enabled during reset. d[7:0] i/o y iohpph low-order data bus ? output drivers are disabled and pull-up resistors are enabled during reset. a[21:0] i/o y iohp address ? input when bgnt is low; otherwise output. twenty- two bits is a 4 mbyte address space. eb [1:0] i/o y iohp byte enable (active low) ? input when bgnt is low; otherwise output. eb0 enables d[15:8] and eb1 enables d[7:0]. when the data bus is configured as an 8-bit bus, eb0 is always released (high) and eb1 is always asserted (low). bw8 i/o y iohpph bus width 8 (open-drain, active low) ? if this pin is driven low either externally or internally, the external bus functions as an 8- bit bus. we i/o y iohp write enable (active low) ? input when bgnt is low. when we is low, data is driven by an external device and received by the mmc2080. output when bgnt is high. when we is low, data is driven by the mmc2080 and received by an external device. oe i/o y iohp output enable (active low) ? input when bgnt is low; when oe is high, d[7:0] (and d[15:8] when in 16-bit mode) external data drivers are disabled. output when bgnt is high; when oe is high, drivers are disabled. ta oy otp transfer acknowledge (active low) ? an external transaction continues when this pin is high. when low, the external data transfer cycle will complete. when monitor mode is set. ta also indicates the end of internal transactions. abort oy otp data transfer abort (active low) ? when a transaction is aborted, this pin is driven low. busclk o y otp external bus clock . sel [3:0] o y otp external device select ? sel0 is always active low; sel[3:1] may be individually programmed as active low or active high. after reset, sel3 is active high. sel1 and sel2 are active low after restart. xboot i y inhpp external boot (active low) ? if this pin is low after a reset, the external boot portion of the system memory map is enabled; otherwise the internal boot map is enabled. irq o y otp interrupt request ? this is driven high when either a normal interrupt or a fast interrupt is generated by the interrupt controller.
24 mmc2080/2075 technical data preliminary tables of signals table 9. development extensions (208-pin package) signal name dir n i/o cell description d[31:16] i/o n iohpph extension to provide a 32-bit external bus. the bus is enabled when either dvl0 or _dvl0 is asserted. dvleb [1:0] i/o n iohpph byte enable (active low) ? input when bgnt is low; otherwise output. dvleb0 enables d[31:24] and dvleb1 enables d[23:16]. dvl [1:0] i n inhpp development mode ? when dvl1 is low, the internal rom is bypassed. if the rom space is addressed when dvl1 is low and xboot is high, the 32-bit extension is enabled and dvlsel is asserted to select an external memory. when dvl0 is low, the 32-bit bus extension is enabled for external bus masters (bgnt is low) and for debug monitor modes. dvlsel on otp development select (active low) ? when dvl1 is low and xboot is high, this output is asserted when the internal rom locations are addressed. dvlmx i n inhpp selects the output of dstat[5:0]. dstat[5:0] o n otp when dvlmx is high, dstat is the low-order 6 bits of the interrupt vector. when dvlmx is low, dstat[3:0] is the m core pipeline status, pstat[3:0], and dstat[5:4] is the transfer size in m core format. tc[2:0] on otp processor transfer code . tea i n inhpp transfer error acknowledge (active low). highz i n inhpp tri-state disable (active low) ? when asserted (low), all tri-state outputs are disabled (high-z). this performs the same function as the jtag highz command. pull_en i n inhpp enable pull-up resistors ? when low, all pull-up resistors (except the pull-up resistor on this i/o cell) are disabled. shs on otp show cycle strobe (active low) ? strobes low when data is valid.
tables of signals signal and connection descriptions 25 preliminary table 10. flex signals (mmc2080 only) signal name dir n i/o cell description lobat in y inhp low battery ? lobat is an input signal to indicate to the mmc2080 when external battery power is going low. (an external voltage sensing circuit is required.) polarity is programmable. exts[1:0] in y iohp external symbol ? exts 1 is the msb of the current flex symbol. exts0 is the lsb of the current flex symbol. these pins are used when demodulation is being performed externally. clkout* o y otp clock output ? clkout is programmable as a 38.4 or 40 khz clock output (derived from oscillator). symclk o y otp recovered symbol clock ? data is synchronized to the internal clock, and this recovered clock output enhances lock-on capability by reducing jitter from cable-induced noise. s[7:1] o y otp control lines 1 ? 7 ? these signals are the seven additional receiver control lines. selectable polarity. s0/ifin i/o y iohp s0 ? this signal is a receiver control output line when the ide bit is clear (that is, the internal demodulator is disabled). ifin ? this signal is a limited if input when the ide bit is set (that is, the internal demodulator is enabled). table 11. fsc/spi1 signals signal name dir n i/o cell description mpe4/lock i/o y iohpph external synthesizer lock input ? pio when spi1 is disabled mpe3/mosi i/o y iohpph master-out / slave-in ? pio when spi1 is disabled mpe2/miso i/o y iohpph master-in / slave-out ? pio when spi1 is disabled mpe1/ss i/o y iohpph slave select (selectable polarity) ? pio when spi1 is disabled mpe0/sclk i/o y iohpph serial clock ? pio when spi1 is disabled table 12. sci signals signal name dir n i/o cell description mpc7/urxd i/o y iohpph receive data ? an input when used as urxd; otherwise a pio mpc6/utxd i/o y iohpph transmit data ? an output when used as utxd; otherwise a pio mpc5/ucts i/o y iohpph clear-to-send (active low) ? an input when used as ucts ; otherwise a pio mpc4/urts i/o y iohpph request-to-send (active low) ? an output when used as urts ; otherwise a pio uclk i/o y iohpph uart clock
26 mmc2080/2075 technical data preliminary tables of signals table 13. timer signals signal name dir n i/o cell description mpc3/tic1 i/o y iohpph timer1 input capture ? an input when used as tic1; otherwise a pio mpc2/toc1 i/o y iohpph timer1 output capture ? an output when used as toc1; otherwise a pio mpc1/tic0 i/o y iohpph timer0 input capture ? an input when used as tic0; otherwise a pio mpc0/toc0 i/o y iohpph timer0 output capture ? an output when used as toc0; otherwise a pio table 14. melody generator signal signal name dir n i/o cell description mldy o y otp melody generator waveform table 15. keypad signals signal name dir n i/o cell description mpb[7:4]/ row[3:0] i/o y iohpph row detect ? inputs when used as row detect; otherwise a pio mpb[3:0]/ col[3:0] i/o y iohpph column select ? open-drain outputs when used as column select; otherwise a pio table 16. mpio signals signal name dir n i/o cell description mpa[5:0] i/o y swiop these bits can be individually programmed as input (with selectable pull-up resistor), output (with selectable drive strength), or external interrupt (with selectable assertion level). each gpio input pin is latched at the beginning of a read cycle. other pins when configured as pio i/o y iohpp h these bits can be individually programmed as input (with selectable pull-up resistor) or output (with selectable drive strength). each mpio input pin is latched at the beginning of a read cycle. table 17. sim signals signal name dir n i/o cell description reset i y inhp external reset (active low) rstout o y otp reset output (active low)
tables of signals signal and connection descriptions 27 preliminary table 20. arbitration signals table 18. jtag/once ? signals signal name dir n i/o cell description tms i y inhpp test mode select ? pull-up resistor always enabled tck i y inhpp test clock ? pull-up resistor always enabled tdi i y inhpp test data in ? pull-up resistor always enabled tdo o y otp test data out trst i y inhp tap reset (active low) de i/o y iohpph debug enable (open drain, active low) table 19. clock and power signal name n i/o cell description extal y ain oscillator circuit input ? external 76.8 khz crystal xtal y aot oscillator circuit output cxfc y ain pll filter capacitor v dd core (5) y power core power v ss core(5) y power core ground v dd io (11) y power i/o pad power v ss io (11) y power i/o pad ground v dd osc y power oscillator power v ss osc y power oscillator ground v dd pll y power pll power v ss pll y power pll ground signal name dir n i/o cell description breq i y inhpp arbitration request (active low) ? request mastership of the internal system bus; pull-up resistor always enabled bgnt oy otp arbitration grant (active low) ? indicates system bus is granted to external master
28 mmc2080/2075 technical data preliminary general characteristics part 3 specifications 3.1 general characteristics the mmc2080/2075 specifications are preliminary, from design simulations, and may not be fully tested or guaranteed at this early stage of the product life cycle. finalized specifications will be published upon the completion of full characterization and device qualifications. 3.2 maximum ratings warning: this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either vss or vdd). note: in the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. a maximum specification is calculated using a worst-case variation of process parameter values in one direction. the minimum specification is calculated using the worst-case variation for the same parameters in the opposite direction. therefore, a ? maximum ? value for a specification will never occur in the same device that has a ? minimum ? value for another specification; adding a maximum to a minimum represents a condition that can never exist. remaining specification information to be provided. table 21. dc absolute maximum operating conditions characteristics symbol min typ max units supply (all) vdd 1.8 3.0 3.6 v input voltage range v i v input clamp current (v 1 <0 or v 1 >qvddh) i i ma output clamp current (v 1 <0 or v 1 >qvddh) i o ma storage temperature range o c
bga details pin-out and package information 29 preliminary part 4 pin-out and package information this section provides information about the available packages for this product. the mmc2080/2075 is available in a 144-pin ball grid array (bga) package. a 208-pin pin grid array (pga) is produced for engineering use only. contact the factory for availability. 4.1 bga details the mmc2080/2075 is offered in the jedec-standard, mold array process (map), 12 mm x 12 mm bga with 0.8 mm ball pitch (0.4 mm small solder balls). refer to figure 8 for the package drawings and dimensions. 4.1.1 bga package mechanical drawings the mechanical drawings for the 144-pin ball grid array package are shown in figure 8. figure 8. mmc2080/2075 bga mechanical drawings 4 z view m-m detail k m a detail k m 0.15 z xy z 0.08 3 b 144x a1 a2 0.10 z 5 0.20 z rotated 90 clockwise dim min max millimeters a 1.25 1.60 a1 0.18 0.34 a2 1.16 ref b 0.35 0.45 d 12.00 bsc e 12.00 bsc e 0.80 bsc notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. 12 e 12x e d laser mark for pin 1 identification in this area x 0.15 metalized mark for pin 1 identification in this area 111098 54321 a b c d e f g h j k l m 13 n e 12x y
30 mmc2080/2075 technical data preliminary pga details 4.2 pga details the mmc2080/2075 is also offered in a ceramic, 43 mm x 43 mm pga for engineering use only. contact the factory for availability. refer to figure 9 for the package drawings and dimensions. 4.2.1 pga package mechanical drawings the mechanical drawings for the 208-pin ball grid pga package are shown in figure 9. figure 9. mmc2080/2075 pga mechanical drawings m 0.500 c m 0.250 c a m ab m b e d l 0.200 c c f g dim min max millimeters d 42.70 43.70 e 42.70 43.70 f 1.78 3.68 g 1.14 1.90 h 0.08 --- k --- 2.00 l 2.54 5.00 b 0.40 0.50 e 2.54 bsc notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. minimum spacing between conductors shall be 0.500. k e 16x a b c d e f g h j k l m n p r t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 u e 16x b 208x h 4x seating plane
ordering drawings pin-out and package information 31 preliminary 4.3 ordering drawings complete mechanical information regarding mmc2080/2075 packaging is available by facsimile through motorola ? s mfax ? system. call the following number to obtain information by facsimile: the mfax automated system requests the following information: the receiving facsimile telephone number, including area code or country code the caller ? s personal identification number (pin) note: for first-time callers, the system provides instructions for setting up a pin, which requires the entry of a name and telephone number. the type of information requested: ? instructions for using the system ? a literature order form ? specific-part technical information or datasheets ? other information described by the system messages a total of three documents may be ordered per call. the mmc2080/2075 144-pin bga package mechanical drawing is referenced as case 1248a-01 rev. 0. the mmc2080/2075 208-pin bga package mechanical drawing is referenced as case 1297-01 rev. 0. (602) 244-6591
32 mmc2080/2075 technical data preliminary heat dissipation part 5 design considerations 5.1 heat dissipation an estimate of the mmc2080/2075 chip junction temperature, t j , in c can be obtained from the following equation. where: t a = ambient temperature c r ja = package junction-to-ambient thermal resistance c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance, as follows: where: r ja = package junction-to-ambient thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise change the thermal dissipation capability of the area surrounding the device on a printed circuit board. this model is most useful for ceramic packages with heat sinks; ninety percent of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device ? s thermal performance may need the additional modeling capability of a system-level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperature of the printed circuit board to which the package is mounted. again, if the estimations obtained from r ja do not satisfactorily answer whether the thermal performance is adequate, a system-level model may be appropriate. a complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: to minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. to define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. if the temperature of the package case (t t ) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (t j - t t )/p d . as noted previously, the junction-to-case thermal resistances quoted in this document are determined using the first definition. from a practical standpoint, this value is also suitable for determining the junction t j t a p d r ja () + = r ja r jc r ca + =
electrical design considerations design considerations 33 preliminary temperature from a case thermocouple reading in forced convection environments. in natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than the actual temperature. hence, the new thermal metric, thermal characterization parameter or jt , has been defined to be (t j - t t )/ p d . this value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. the recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. note: section 3, ? specifications, ? on page 28 of this document contains the package thermal values for this chip. 5.2 electrical design considerations warning: this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either vss or v dd ). use the following list of recommendations to assure correct operation: provide a low-impedance path from the board power supply to each vdd pin on the mmc2080/ 2075 and from the board ground to each vss pin. use at least four 0.1 f bypass capacitors positioned as close as possible to the four sides of the package to connect the vdd power source to vss. ensure that capacitor leads and associated printed circuit traces that connect to the chip vdd and vss pins are less than 0.5 inch per capacitor lead. use at least a four-layer printed circuit board (pcb) with two inner layers for vdd and vss. consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the vdd and vss circuits. all inputs must be terminated (that is, not allowed to float) using cmos levels. take special care to minimize noise levels on the pll supply pins (both vdd and vss).
once, m core, mfax, roaming flex, flex alphanumeric chip, flex chip, flex numeric chip, and flex stack are trademarks of motorola, inc. this document contains information on a new product. specifications and information herein are subject to change without notice. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation consequential or incidental damages. ? typical ? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ? typicals ? must be validated for each customer application by customer ? s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in wh ich the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers , employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. all other tradenames, trademarks, and registered trademarks are the property of their respective owners. how to reach us: usa/europe/locations not listed : motorola literature distribution; p.o. box 5405, denver, colorado, 80217 1-303-675-2140 or 1-800-441-2447 japan : motorola japan, ltd.; sps, technical information center, 3-20-1, minami-azabu, minato-ku, tokyo 106-8573 japan. 81-3-3440-3569 asia/pacific : motorola semiconductors h.k. ltd., silicon harbour centre, 2 dai king street, tai po industrial estate, 2 tai po, n.t., hong kong. 852-26668334 customer focus center: 1-800-521-6274 mfax ? : rmfax0@email.sps.mot.com ? touchtone 1-602-244-6609 ? us & canada only 1-800-774-184 ? http://sps.motorola.com/mfax/ home page: http://motorola.com/sps motorola dsp products home page: http://www.motorola-dsp.com mmc2080/2075/d

▲Up To Search▲

Price & Availability of MMC2080VF001

	To Download MMC2080VF001 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .